Ultra-low power incremental delta-sigma analog-to-digital converter for self-powered sensor applications

Tässä työssä esitetään ultramatalatehoinen inkrementaalinen delta-sigma-analogia-digitaalimuunnin. Muunnin on suunniteltu 0,18 μm:n CMOS-teknologialla, ja se toimii 1,2 V :n käyttöjännitteellä ja 5 kHz:n kellotaajuudella. Differentiaalinen tulosignaali on käytännössä dc:llä, ja se vaihtelee 600 mV :n yhteismuotoisen jännitteen ympärillä -850 mV :sta 850 mV :iin. Delta-sigmamodulaattorissa käytetään kaksiasteista takaisinkytkettyä integraattorikaskadirakennetta, joka on toteutettu kytketty-kondensaattori-integraattoreilla ja yksibittisellä kvantisoijalla. Muuntimen kvantisointikohinavaatimuksien täyttyminen varmistettiin valitsemalla sopivat kertoimet ja ylinäytteistyssuhde käyttäen MATLAB-simulaatioita yhdessä modulaattorin ideaalisen mallin kanssa. Vahvistinten vähimmäisvaatimukset määritettiin makromallitason simuloinneilla ja kytkinten epäideaalisuudet analysoitiin transistoritason simuloinneilla. Varausinjektion huomattiin aiheuttavan piirissä merkittävää harmonista säröä, joten alalevyn näytteistystä (bottom plate sampling) käytettiin signaaliriippuvan varausinjektion välttämiseksi. Lisäksi ensimmäisen integraattorin vahvistimen tulonsiirrosjännitteen ja matalataajuisen kohinan vähentämiseksi käytettiin hakkuristabilointia (chopper stabilization). Muuntimen suorituskykyä analysoitiin eri prosessikulmissa lämpötiloissa −40 ◦ C, 27 ◦ C ja 85 ◦ C, ja epäsovitusherkkyys määritettiin Monte Carlo -analyysin avulla. Simulaatiotulokset sekä piirikuvion perusteella lasketut parasiittiset resistanssit ja kapasitanssit huomioonottaen, että ilman, osoittavat piirin olevan stabiili ja täyttävän tarkkuusvaatimukset kaikissa simuloiduissa kulmissa. Monta Carlo -analyysin perusteella signaali-kohinasuhde on vähintään 80,05 dB:ä ja harmonisen särön kokonaismäärä on enintään -80.89 dB:ä. Tehonkulutus ei ylitä 1,2 μA:a missään simulaatiossa.In this thesis an ultra-low power incremental delta-sigma analog-to-digital converter is presented. The converter is designed in 0.18 μm CMOS technology with a single 1.2 V supply voltage, and it operates with a 5 kHz clock signal. The differential input signal to the converter is virtually dc, and it varies from −850 mV to 850 mV around a common-mode voltage of 600 mV . The delta-sigma modulator has a second order cascade-of-integrators feedback structure, which is realized with switched-capacitor integrators and a one-bit quantizer. The converter’s quantization noise requirement is met by appropriate choice of coefficients and oversampling ratio, based on MATLAB simulations on an ideal model of the modulator. The minimum requirements of the amplifiers were determined from simulations with macromodels, and the switch non-idealities were analyzed in transistor-level simulations. It was noticed that switch charge injection causes significant harmonic distortion in the circuit, hence bottom plate sampling was implemented to eliminate the signal-dependent charge injection. Furthermore, the offset and low-frequency noise in the first integrator were attenuated by means of chopper stabilization. The converter’s performance is analyzed in different process corners, at −40◦ C, 27◦ C, and 85◦ C, and its process mismatch sensitivity is determined via Monte Carlo analysis. The results obtained from both pre- and post-layout simulations indicate complete stability, and acceptable accuracy in all design corners. The minimum signal-to-noise and distortion ratio obtained from corner analysis, is 80.05 dB, which is enhanced up to 7 dB in the best corner, and maximum harmonic distortion is below −80.89 dB. Moreover, the power consumption of the converter did not exceed 1.2 μW in any of the simulations

Jitter Suppression Techniques for High Speed Communication Systems

University of Minnesota Ph.D. dissertation. December 2019. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); 98 pages.The drive towards fast and robust communication has resulted in an increased focus on high frequency analog and digital transceivers. One of the major challenges in high-speed analog transceivers, is the front-end analog-to-digital converter (ADC). All ADCs rely on periodic samples of the input signal. To enable high accuracy analog to digital conversion at high frequencies, a clean sampling clock is required. However, the non-idealities in the clock generation and distribution system can result in uncertainties in the sampling edges of the clock signal. These uncertainties are referred to as jitter. In many cases, the jitter requirement on the sampling clock is less than 100 fs, rms, realizing which is not trivial. More important, there exists a disconnect between the clock designers and the ADC designers, when it comes to jitter suppression. While clock designers are focused on minimizing the narrow-band clock jitter, the ADC designers have to deal with the broadband noise in the clock path, which is detrimental to the ADC's performance. The question we try to answer in this thesis is, whether rather than tackling the jitter at the source, one can reduce the jitter sensitivity of the ADCs by using jitter-resilient sampling techniques. A review of various sources of jitter, and the impact of jitter on analog and digital transceivers is presented. This facilitates the understanding, characterizing, and ultimately reducing the jitter-induced errors in the communication systems. A new sampling technique, called Delta Sigma sampling, is proposed to suppress the jitter induced sampling error in ADCs. The design uses a Delta Sigma architecture with low oversampling ratio (OSR) to shape the jitter error, in the same way that a Delta Sigma ADC shapes the quantization error. The Delta Sigma sampler, however, does not have a quantizer, and as a result, the output of the sampler is a sampled-and-held signal. Therefore, a Delta Sigma sampler can be used as a jitter-resilient front-end for any type of ADC. To prove the functionality of the proposed sampling technique, a comprehensive time-domain analysis is presented. In this analysis, 1st-, 2nd-, and higher order Delta Sigma samplers with various feedback architectures are considered. The feedback architectures include return-to-zero (RZ), non return-to-zero (NRZ), and switched-capacitor. Three sources of jitter are identified in the sampler: the sampling clock jitter, the feedback pulse edge jitter, and the feedback pulsewidth variations. We show that first, the switched-capacitor feedback impairs the jitter shaping properties of the loop. In fact, the decaying nature of the pulse reduces the loop order to N-1. Second, a 1st-order Delta Sigma sampler has the same signal-to-jitter noise ratio (SJNR) with switched-capacitor feedback, and with constant-pulsewidth RZ feedback. RZ feedback relaxes the slew rate requirements of the integrator, thereby reducing the power consumption of the system. However, the feedback pulsewidth variations degrade the SJNR significantly. A new clocking scheme, called correlated clocking, is introduced to alleviate the pulsewidth jitter of the RZ feedback. This technique uses the correlation between the rising and falling edges of the feedback clock to minimize the feedback pulsewidth variations. The proposed clocking technique can also be used in continuous-time Delta Sigma ADCs. The analysis indicates that the maximum SJNR benefit of a Delta Sigma sampler over a Nyquist sampler is equal to 10*log10(OSR)+4.77 dB. That is equivalent to a 4X reduction of clock jitter in a Nyquist sampler or 3X increase in OSR for an oversampler. The maximum SJNR is independent of the loop order and the feedback architecture, and it stays constant for OSR >5. Finally, we show that in contrary to the common belief, the feedback edge jitter dominates the overall jitter in the 2nd- and higher-order samplers, as it translates into feedback pulsewidth variations at the output of the second integrator. This error gets 1st-order shaped, regardless of the loop order, making it the dominant source of jitter in higher order Delta Sigma loops. The theoretical analysis is veried by numerical simulations in MATLAB and behavioral simulations in Cadence. In addition, a 5 GS/s 1st-order Delta Sigma sampler with correlated clocking is implemented in 65 nm CMOS technology, and verified through circuit-level simulations in Cadence